Semiconductor structures with structural homogeneity

ABSTRACT

Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.

RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser.No. 60/442,784, filed on Jan. 27, 2003, the entire disclosure of whichis hereby incorporated by reference.

FIELD OF THE INVENTION

This invention relates generally to semiconductor substrates andparticularly to substrates with strained semiconductor layers.

BACKGROUND

“Virtual substrates” based on silicon (Si) and germanium (Ge) provide aplatform for new generations of very large scale integration (VLSI)devices that exhibit enhanced performance in comparison to devicesfabricated on bulk Si substrates. The important component of a SiGevirtual substrate is a layer of SiGe that has been relaxed to itsequilibrium lattice constant (i.e., one that is larger than that of Si).This relaxed SiGe layer may be directly applied to a Si substrate (e.g.,by wafer bonding or direct epitaxy), or atop a relaxed graded SiGebuffer layer in which the lattice constant of the SiGe material has beenincreased gradually over the thickness of the layer. The SiGe virtualsubstrate may also incorporate buried insulating layers, in the mannerof a silicon-on-insulator (SOI) wafer. To fabricate high-performancedevices on these platforms, thin strained layers of semiconductors, suchas Si, Ge, or SiGe, are grown on the relaxed SiGe virtual substrates.The resulting biaxial tensile or compressive strain alters the carriermobilities in the layers, enabling the fabrication of high-speed and/orlow-power-consumption devices. The thin strained semiconductor layersmay also be subsequently transferred to other substrates havinginsulator layers by methods such as wafer bonding, thus creatingstrained-semiconductor-on-insulator (SSOI) wafers.

In certain cases the microstructure of semiconductor graded bufferlayers as grown may be less than ideal depending on the growthconditions. For example, SiGe buffer layers deposited at temperaturesbelow 850° C. may not attain the relaxation state desired for strainedSi applications, i.e., >98%. In addition, the density of threadingdislocations may be higher than desired. Furthermore, both high and lowtemperature growth conditions may result in as-grown graded bufferlayers having top surfaces that are rougher than the ultra-planarsurfaces preferable for growth of relaxed semiconductor cap layers withsubsequent strained semiconductor layer deposition (e.g., regrowth ofSiGe layers containing 20% Ge, followed by deposition of strained Si).This roughness may carry over and increase in subsequently formedlayers. In addition, roughness on a layer surface negatively impacts theability of laser scanning tools to perform optical inspection fordefects in the layer before and after planarization and regrowth.Roughness appears in the scattered signal of the laser scanner as anelevated level of “haze” or background noise, reducing the ability ofthe tool to detect small defects in and on the layer. It is desirable,therefore, to reduce this roughness in semiconductor layers.

SUMMARY

One technique suitable for fabricating strained Si wafers may includethe following steps:

-   -   1. Providing a silicon substrate;    -   2. Epitaxially depositing a relaxed, graded SiGe buffer layer to        some final Ge composition on the silicon substrate;    -   3. Epitaxially depositing a relaxed SiGe cap layer having a        constant composition on the SiGe buffer layer;    -   4. Annealing the layers at a temperature greater than a growth        temperature of the layers to relax strain or modify the        morphology of the layers, at any point during or after Steps 2        and 3;    -   5. Planarizing a surface of the SiGe cap layer by, e.g.,        chemical mechanical polishing (CMP), and cleaning the resulting        planarized surface;    -   6. Epitaxially depositing a relaxed SiGe regrowth layer having a        constant composition on the planarized surface; and    -   7. Epitaxially depositing a strained Si layer on the SiGe        regrowth layer.    -   8. Measuring the surface quality of the strained Si layer using        laser scanning techniques.

Annealing at elevated temperatures may improve the properties of layersdeposited at relatively low temperatures, e.g., below 850° C. Variouslayer properties, in addition to relaxation and threading dislocationdensities, are important for making strained semiconductor layers, e.g.,strained silicon layers. For example, at high temperature growthconditions (>850° C.), graded and constant composition SiGe bufferlayers may contain microstructural phenomena such as decomposition.Decomposition may sometimes be observed as narrow vertical bands ofvarying composition, i.e., vertical superlattices.

Elevated temperature annealing before, after, or between planarizationprocess steps may be used to improve the microstructure of semiconductorlayers. Compositional variation within layers is reduced, therebyenabling the formation of layers with top surfaces that remain smootheven after cleaning steps that etch different compositions at differentrates.

In some embodiments, compositional superlattices may be avoided byappropriate selection of semiconductor layer growth parameters andregrowth layer parameters.

In an aspect, the invention features a method for forming asemiconductor structure, the method including providing a substrate, andforming a semiconductor layer over a top surface of the substrate, thesemiconductor layer including at least two elements, the elements beingdistributed to define an initial compositional variation within thesemiconductor layer. The semiconductor layer is annealed to reduce theinitial compositional variation.

One or more of the following features may be included. The substrate mayhave a first lattice constant, the semiconductor layer may have a secondlattice constant, and the first lattice constant may differ from thesecond lattice constant. The first element may have a firstconcentration, a second element may have a second concentration, andeach of the first and second concentrations may be at least 5%. Theinitial compositional variation may vary periodically within thesemiconductor layer in a direction perpendicular to a semiconductorlayer deposition direction. The compositional variation may define acolumn within the semiconductor layer, the column having a width and aperiod. The columnar period may be less than approximately 2000nanometers (nm), e.g., less than approximately 1000 nm.

The semiconductor layer may be annealed at an annealing temperatureand/or for a duration sufficient to diffuse at least one of the twoelements through a diffusion length at least equal to a quarter of thecolumnar period.

The initial compositional variation may vary in a direction parallel toa semiconductor layer deposition direction and define a superlatticehaving a periodicity. The superlattice periodicity may be less thanapproximately 100 nm, preferably less than approximately 50 nm, and morepreferably less than approximately 10 nm. The semiconductor layer may beannealed at an annealing temperature sufficient to diffuse at least oneof the two elements through a diffusion length at least equal to aquarter-period of the superlattice and/or for a duration sufficient todiffuse at least one of the two elements through a diffusion length atleast equal to a quarter-period of the superlattice.

The semiconductor layer may be annealed at an annealing temperaturegreater than the deposition temperature. The annealing temperature maybe greater than about 800° C., e.g., greater than about 1000° C.

The semiconductor layer may be annealed at an annealing temperaturebelow a melting point of the semiconductor layer, e.g., less than about1270° C.

At least one of the at least two elements may be silicon and/orgermanium. A top surface of the semiconductor layer may be planarized.The top surface of the semiconductor layer may be planarized before,while, or after the semiconductor layer is annealed. Planarizing mayinclude chemical-mechanical polishing, plasma planarization, wetchemical etching, gas-phase chemical etching [preferably at elevatedtemperature, e.g., above 900° C., in an ambient including an etchspecies, e.g., hydrogen chloride (HCl)], oxidation followed bystripping, and/or cluster ion beam planarization.

Chemical-mechanical polishing may include a first and a second step andthe semiconductor layer may be annealed between the first and the secondchemical-mechanical polishing steps and/or before the firstchemical-mechanical polishing step. The planarization may include a hightemperature step and the semiconductor layer may be annealed during thehigh temperature planarization step.

A top surface of the semiconductor layer may be bonded to a wafer, andat least a portion of the substrate may be removed, such that at least aportion of the semiconductor layer remains bonded to the wafer after theportion of the substrate is removed.

A second layer may be formed over the semiconductor layer subsequent toplanarizing the top surface of the semiconductor layer. The second layermay include a material having a lattice constant substantially equal toor substantially different from a lattice constant of the semiconductorlayer. A top surface of the second layer may be bonded to a wafer and atleast a portion of the substrate may be removed, such that at least aportion of the second layer remains bonded to the wafer after theportion of the substrate is removed.

A second layer may be formed over the semiconductor layer subsequent toplanarizing the top surface of the semiconductor layer. The second layermay include a material having a lattice constant substantially equal toor substantially different from a lattice constant of the semiconductorlayer. A top surface of the second layer may be bonded to a wafer, andat least a portion of the substrate may be removed, with at least aportion of the second layer remaining bonded to the wafer after theportion of the substrate is removed. The second layer may include (i) alower portion having a superlattice and (ii) an upper portion disposedover the lower portion, the upper portion being substantially free of asuperlattice.

The semiconductor layer may have an undulating surface. The undulatingsurface may be formed during deposition of the semiconductor layer. Thesubstrate may have an undulating substrate surface, and the undulatingsubstrate surface induces the formation of the undulating surface of thesemiconductor layer. The undulating surface may have an amplitude, theinitial compositional variation may define a superlattice having aperiodicity, and the periodicity of the superlattice may be less thanthe amplitude of the undulating surface.

A relaxed graded layer may be formed over the substrate, such that thesemiconductor layer is formed over the relaxed graded layer. The relaxedgraded layer may serve to provide the semiconductor layer with a latticespacing different from that of the substrate while reducing defectnucleation. A protective layer may be formed over the semiconductorlayer prior to annealing the semiconductor layer. The protective layermay include a material that is substantially inert with respect to thesemiconductor layer, such as, for example, silicon dioxide or siliconnitride. The anneal may be performed as a batch process on multiplewafers at once, for example, in a tube furnace, to improve throughputand economics.

In another aspect, the invention features a method for forming asemiconductor structure, including providing a substrate, and selectinga first plurality of parameters suitable for forming a semiconductorlayer over a top surface of the substrate, the semiconductor layerincluding at least two elements, the elements being distributed todefine a compositional variation within the semiconductor layer. Thesemiconductor layer having a haze is formed, and the semiconductor layeris planarized to remove the haze.

One or more of the following features may be included. Forming thesemiconductor layer may include forming a lower portion having asuperlattice, and forming an upper portion over the lower portion, theupper portion being substantially free of a superlattice. The firstplurality of parameters may include temperature, precursor, growth rate,and/or pressure. The semiconductor layer may be cleaned afterplanarizing, with the semiconductor layer remaining substantiallyhaze-free after cleaning. A second plurality of parameters may beselected that is suitable for forming a substantially haze-free regrowthlayer over the semiconductor layer, the semiconductor layer including atleast two elements, the elements being distributed to define acompositional variation within the semiconductor layer. Thesubstantially haze-free regrowth layer may be formed. The firstplurality of parameters may include a first temperature, the secondplurality of parameters may include a second temperature, and the firsttemperature may be higher than the second temperature. The firstplurality of parameters include a first growth rate, the secondplurality of parameters may include a second growth rate, and the firstgrowth rate may be higher than the second growth rate. Forming theregrowth layer may include forming a lower portion having a superlatticeand forming an upper portion over the lower portion, the upper portionbeing substantially free of a superlattice.

In another aspect, the invention features a semiconductor structureincluding a substrate, and a semiconductor layer disposed over thesubstrate, the semiconductor layer including at least two elements andhaving a top surface. The semiconductor layer top surface issubstantially haze-free.

One or more of the following features may be included. A portion of thesemiconductor layer disposed below the top surface may include asuperlattice. A relaxed graded layer may be disposed between thesubstrate and the semiconductor layer. The semiconductor layer topsurface may have a roughness root-mean-square of less than 10 angstroms(Å), preferably less than 5 Å in a scan area of 40 μm×40 μm, and acontamination level of less than 0.29 particles/cm², the particleshaving a diameter greater than 0.12 micrometers (μm). Preferably, theroughness is less than 1 Å root-mean-square in a scan area of 1 μm×1 μm.

The semiconductor layer top surface may have a roughness of less than 10Å, preferably less than 5 Å root-mean-square in a scan area of 40 μm×40μm and a contamination level of less than 0.16 particles/cm², theparticles having a diameter greater than 0.16 μm. Preferably, theroughness is less than 1 Å root-mean-square in a scan area of 1 μm×1 μm.

The semiconductor layer top surface may have a roughness of less than 10Å, preferably less than 5 Å root-mean-square in a scan area of 40 μm×40μm and a contamination level of less than 0.08 particles/cm², theparticles having a diameter greater than 0.2 μm. Preferably, theroughness is less than 1 Å root-mean-square in a scan area of 1 μm×1 μm.

The semiconductor top surface may have a roughness of less than 10 Å,preferably less than 5 Å root-mean-square in a scan area of 40 μm×40 μmand a contamination level of less than 0.019 particles/cm², theparticles having a diameter greater than 1 μm. Preferably, the roughnessis less than 1 Å root-mean-square in a scan area of 1 μm×1 μm.

The semiconductor layer top surface may have a roughness of less than0.5 Å root-mean-square in a scan area of 1 μm×1 μm and a contaminationlevel of less than 0.09 particles/cm², the particles having a diametergreater than 0.09 μm.

In another aspect, the invention features a semiconductor structureincluding a substrate, and a semiconductor layer disposed over thesubstrate, the semiconductor layer including at least two elements. Aregrowth layer is disposed over the semiconductor layer, the regrowthlayer having a top surface that is substantially haze-free.

One or more of the following features may be included. The regrowthlayer may include a semiconductor material, such as silicon. Theregrowth layer may be strained. A portion of the regrowth layer disposedbelow the regrowth layer top surface may include a superlattice.

In another aspect, the invention features a semiconductor structureincluding a wafer, and a semiconductor layer bonded to the wafer, thesemiconductor layer having a top surface that is substantiallyhaze-free.

One or more of the following features may be included. The semiconductorlayer may include silicon and/or germanium. The semiconductor layer maybe strained. The wafer may include an insulating layer. The insulatinglayer may include silicon dioxide.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-6 and 8-11 are schematic cross-sectional views of semiconductorsubstrates illustrating superlattices, columnar structures, andprocesses for forming homogeneous, smooth semiconductor layers; and

FIG. 7 is a diagram illustrating the temperature and time dependence ofdiffusion of Ge in Si.

DETAILED DESCRIPTION

Roughness on semiconductor graded buffer layers may be separated intotwo components, each with distinct characteristics. A first component isa cross-hatch that arises from strain fields created by the formation ofmisfit dislocations. Cross-hatch has the form of a network ofperpendicular waves with several characteristic wavelengths. For manygraded buffer layers formed on wafers, for example layers constituted ofgroup IV or III-V semiconductors with diamond cubic or zinc blendecrystal structures, this cross-hatch is generally oriented in the <110>in-plane direction of the wafers. This relatively widely spacedcomponent of surface texture may be likened to a surface featurereferred to in the SEMI Specifications as “waviness.” A secondcomponent, present in different degrees depending on the growthconditions, is small-scale roughness with no obvious directionality, asmaller amplitude, and a shorter spatial wavelength than thecross-hatch. This fine-scale roughness may be a major contributor tohaze measured on semiconductor layers by laser defect scanning tools.Methods for reducing or eliminating both cross-hatch and fine scaleroughness are described below.

Referring to FIG. 1, an epitaxial wafer 8 has a plurality of layers 10disposed over a substrate 12. Substrate 12 may be formed of asemiconductor, such as Si, Ge, or SiGe. Substrate 12 may also include aninsulator layer (not shown). The plurality of layers 10 formed on a topsurface 13 of substrate 12 includes a graded buffer layer 14, which maybe relaxed and may be formed of Si_(1-y)Ge_(y), with a maximum Gecontent of, e.g., 10-100% (i.e., y=0.1-1.0) and a thickness T₁ of, forexample, greater than or equal to 0.5 μm, e.g., 0.5-10 μm. Asemiconductor layer 16 is disposed over graded buffer layer 14.Semiconductor layer 16 may be relaxed, and may contain at least twoelements. The substrate may have a first lattice constant and thesemiconductor layer 16 may have a second lattice constant, such that thefirst lattice constant differs from the second lattice constant. Thefirst element may have a first concentration and the second element mayhave a second concentration, and each of the first and secondconcentrations may be greater than 5%. The two elements may be, forexample, silicon and germanium (e.g., Si_(1-x)Ge_(x)). Si_(1-x)Ge_(x)may have a Ge content of, for example, 10-100% (i.e., x=0.1-1.0), and athickness T₂ of, for example, 0.2-2 μm. In some embodiments,Si_(1-x)Ge_(x) may include Si_(0.80)Ge_(0.20) and T₂ may beapproximately 1.5 μm. Semiconductor layer 16 may be >90% relaxed, asdetermined by triple axis x-ray diffraction, and may have a threadingdislocation density of <1×10⁶ cm⁻², as determined by etch pit density(EPD) and plan-view transmission electron microscopy (PVTEM) analysis.

Graded layer 14 and semiconductor layer 16 may be formed by epitaxy,such as by atmospheric-pressure chemical vapor deposition (APCVD), low-(or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), orby molecular beam epitaxy (MBE). The epitaxial deposition system may bea single-wafer or multiple-wafer batch reactor. The growth system mayinclude a horizontal flow reactor, in which process gases are introducedinto the reactor from one side and exit the reactor from another side,after passing over one or more substrates. The growth system may alsoutilize a low-energy plasma to enhance layer growth kinetics. Thedeposition temperature may be 500-1200° C.

Substrate 12, graded layer 14, and semiconductor layer 16 may be formedfrom various materials systems, including various combinations of groupII, group III, group IV, group V, and group VI elements. For example,each of substrate 12, graded layer 14, and semiconductor layer 16 mayinclude a III-V compound. Substrate 12 may include gallium arsenide(GaAs), and graded layer 14 and semiconductor layer 16 may includeindium gallium arsenide (InGaAs) or aluminum gallium arsenide (AlGaAs).These examples are merely illustrative, and many other material systemsare suitable.

In alternative embodiments, semiconductor layer 16 is tensilely strained(e.g., Si_(x)Ge_(1-x) disposed over SiyGe_(1-y) where y<x). In otherembodiments, semiconductor layer 16 is compressively strained (e.g.,Si_(x)Ge_(1-x) disposed over SiyGe_(1-y) where y>x). In these cases,semiconductor layer 16 may be disposed over a relaxed semiconductorlayer. In some embodiments, a strained layer (not shown) may be formedon a top surface of semiconductor layer 16 or graded layer 14.

Referring to FIG. 2 as well as to FIG. 1, as deposited, a distributionof the elements from which semiconductor layer 16 is formed may have aninitial compositional variation 20. For example, if semiconductor layer16 includes 20% Ge (Si_(0.80)Ge_(0.20)), the actual Ge concentrationwithin layer 16 may vary by a total of 4%, e.g., 18-22%. This initialcompositional variation 20 may vary in semiconductor layer 16 in adirection parallel to a deposition direction 22 thereof.

Compositional variation 20 may define a superlattice 24 having aperiodicity P₁. Superlattice 24 has alternating regions with low 28 andhigh 29 concentrations of an element, e.g., Ge, alternating in the samelayer, such as in semiconductor layer 16. Such alternation may occur ina horizontal flow deposition reactor, in which a higher fraction of anelement is incorporated at a leading edge of a substrate, i.e., an edgeof wafer 8. The element fraction, e.g., Ge concentration, may alternatevertically within semiconductor layer 16 because substrate 10 may berotated during deposition, thus changing the leading edge first exposedto gas flow. Depending on deposition parameters, alternatingcompositions within a layer may also occur in layers formed in othertypes of deposition systems. Superlattice 24 may have a superlatticeperiodicity P₁. Periodicity P₁ may be less than approximately 100 nm,including less than 50 nm or less than 10 nm. In an embodiment,periodicity P₁ may be 8 nm with, e.g., region 29 having a thickness of 4nm with Ge concentration above, e.g., 20% and region 28 having athickness of 4 nm with Ge concentration below, e.g., 20%.

Referring to FIG. 3, semiconductor layer 16 may be formed over gradedbuffer layer 14 having a top surface 15 that may not be completelysmooth, i.e., it may have cross-hatch formed by strain fields arisingfrom the formation of misfit dislocations. A cross-hatch may have, forexample, a relatively high Ge concentration at a peak and a relativelylow Ge concentration in a trough. Cross-hatch may have a wavelength of1-10 μm and an amplitude of 1-100 nm. Graded buffer layer surface 15 mayalso have fine-scale roughness, with a wavelength of, e.g., 10-100 nmand a height of 1-50 Å. Both cross-hatch and fine-scale roughness maycarry over to cause undulation 30 in a top surface 32 of semiconductorlayer 16. Undulation 30 may be formed during deposition of semiconductorlayer 16. Undulation 30 has an amplitude A that may be greater thanperiodicity P₁ of superlattice 24.

Referring to FIG. 4, semiconductor layer surface 32 may be planarizedby, e.g., CMP. Planarization exposes lateral composition variations onplanarized semiconductor layer surface 32. The periodicity P₁ ofelements disposed in semiconductor layer 16, i.e., superlattice 24,however, may cause problems with subsequent processing. For example,maintaining the planarity of semiconductor layer 16 may be challenging.Cleaning steps after planarization may re-roughen surface 32. A wetcleaning solution whose removal rate is compositionally dependent mayresult in a rough top surface if there is lateral compositionalvariation in the layer being cleaned and the removal rate iscompositionally dependent. Such a solution may, for example, selectivelyetch portions of layer 16 with higher concentrations of a particularelement, such as region 29 having a higher concentration of, e.g., Ge,more quickly than portions of layer 16 with a lower concentration of thesame element, such as region 28 having a lower concentration of, e.g.,Ge. An example of such a wet etch is RCA SC1, i.e., ammonium hydroxide,hydrogen peroxide, and deionized water at a ratio of, e.g., 1:1:10 or1:1:100, at 40-80° C. for about 10 minutes, with or without megasonicagitation.

Referring to FIG. 5, in an alternative embodiment, initial compositionalvariation 20 may vary in semiconductor layer 16 in a directionperpendicular to the deposition direction 22 thereof. Initialcompositional variation 20 may define a column 50 within semiconductorlayer 16. Column 50 may have an irregular cross-section. Column 50 mayform as a result of an interaction between the cross-hatch formed onsurface 15 of graded layer 14 and superlattice 24 (see, e.g., FIGS.2-4). This interaction may cause decomposition during the formation ofsemiconductor layer 16, resulting in the formation of a plurality ofcolumns 50 having a relatively high concentration of an element, e.g.,Ge, alternating with a plurality of columns 52 having a relatively lowconcentration of the same element. Column 50 and column 52 may each havea width W₁ less than approximately 1000 nm, such that columnar periodP₂, including column 50 and column 52 (one dark region and one lightregion in FIG. 5) is less than approximately 2000 nm. In someembodiments, columnar period P₂ may be less than 1000 nm. Semiconductorlayer surface 32 may be planarized, e.g., by CMP. The presence ofcolumns 50, 52 with varying compositions in semiconductor layer 16,however, may cause problems with subsequent processing. For example,maintaining the planarity of semiconductor layer 16 may be challenging.Cleaning steps after planarization may re-roughen surface 32. Cleaningsolutions, such as RCA SC1 may selectively etch faster portions of layer16 with higher concentrations of a particular element, such as columns50 having a higher concentration of, e.g., Ge than portions of layer 16with lower concentrations of the same element, such as columns 52 havinga lower concentration of, e.g., Ge.

Referring to FIG. 6, the initial compositional variation withinsemiconductor layer 16 may be reduced by annealing semiconductor layer16. The resulting reduction of the initial compositional variation maysubstantially eliminate superlattice 24, as well as columns 50, 52,resulting in a relatively homogeneous compositional distribution withinsemiconductor layer 16. The relatively uniform composition ofsemiconductor layer 16 reduces the aforementioned effects of cleaningsteps, i.e., non-uniform etch rates of semiconductor layer 16 regionswith varying compositions, resulting in roughening of semiconductorlayer surface 32. Annealing may increase the amplitude and wavelength ofthe cross-hatch, but reduces the short wavelength roughness. Thecross-hatch may have a wavelength sufficiently long so that a smallincrease in the long wavelength roughness (>1 μm) may not affect opticalscanning measurements of semiconductor layer surface 32.

Referring to FIGS. 3 and 6, the annealing temperature may be sufficientto diffuse at least one of the at least two elements included insemiconductor layer 16 through a diffusion length at least equal toone-quarter the period P₁ of superlattice 24, in a cost-effective time.For example, to diffuse Ge through a diffusion length of 100 nm, theannealing temperature may be at least 850° C. at a duration of 300,000seconds (83.3 hours). This temperature and duration may be derived fromthe following equations. The diffusion length x may be calculated by:

x=2*(Dt)^(0.15)  (Equation 1)

where

x is the characteristic diffusion length,

D is the characteristic diffusion coefficient of one of the at least twoelements in another of the at least two elements, and

t is the diffusion time.

The diffusion coefficient D is given by the following:

D=D _(o) exp(−E/kT)  (Equation 2)

where

D_(o) is the pre-exponential factor,

E is the activation energy,

k is the Boltzmann constant, and

T is the annealing temperature (in degrees Kelvin).

For example, for germanium diffusing in silicon, the following valuesmay be obtained from published literature: D_(o)=6.26×10^(5 cm) ²/sec,E=5.28 eV, and k=8.63×10⁻⁵ eV/K. Using these values, the characteristicdiffusion distance may be calculated for a range of anneal times, andplotted versus temperature (see, e.g., FIG. 7). The various values ofthe diffusion constants for germanium in silicon that are available mayproduce somewhat different results (see below). In some embodiments, theduration of the anneal is selected to be sufficient to diffuse at leastone of the at least two elements included in semiconductor layer 16through a diffusion length at least equal to a quarter of the period P₁of superlattice 24, at an acceptable temperature, i.e., a temperaturehigh enough to provide adequate throughput without damaging thesubstrate or melting semiconductor layer 16. This temperature may begreater than about 800° C. and less than about 1270° C. For example, todiffuse Ge through a diffusion length of at least 100 nm, the durationof the annealing may be at least 12 seconds at a temperature of 1250° C.This duration may be derived from equations 1-2 and/or FIG. 7. Referringto FIGS. 5 and 6, the annealing temperature may be sufficient to diffuseone or more of the elements included in semiconductor layer 16 through adiffusion length at least equal to a quarter of the columnar period P₂(in an economically acceptable time). For example, to diffuse Ge througha diffusion length of at least 1000 nm, the annealing temperature may beat least 1050° C. at a duration of 300,000 sec (83.3 hours). Theappropriate annealing temperature may be derived from the equations 1-2above or FIG. 7. In some embodiments, the duration of the anneal may beselected to be sufficient to diffuse at least one of the at least twoelements included in semiconductor layer 16 through a diffusion lengthat least equal to a quarter of the columnar period P₂. For example, todiffuse Ge through a diffusion length of at least 1000 nm, the durationof the annealing may be at least 1200 sec (20 minutes) at a temperatureof 1250° C. This duration may be derived from equations 1-2 and/or FIG.7.

Referring to FIGS. 3, 5, and 6, in some embodiments, semiconductor layer16 is annealed at an annealing temperature greater than a depositiontemperature of semiconductor layer 16. For example, the annealingtemperature may be greater than about 800° C., or greater than about1000° C. The annealing temperature may also be less than a melting pointof semiconductor layer 16. For example, for semiconductor layer 16including Si_(0.8)Ge_(0.2), the annealing temperature may be less thanabout 1270° C. A dislocation density in semiconductor layer 16 mayremain substantially unchanged during the annealing step.

Referring to FIG. 6, after an annealing step, semiconductor layer 16 hasa relatively homogeneous compositional distribution. Top surface 32 ofsemiconductor layer 16 may be planarized. This planarization may beperformed before, during, or after the annealing step. Planarization maybe performed by one of several methods, including CMP, plasmaplanarization, wet chemical etching, gas-phase chemical etching(preferably at elevated temperature, e.g., above 900° C., in an ambientincluding an etch species, e.g., HCl), oxidation followed by stripping,and cluster ion beam planarization. In some embodiments, CMP includes afirst (stock) and a second (final) step. The stock polish removes alarger fraction of the total amount of material to be removed (˜0.5 μm)and leaves a semi-polished surface. The final polish step removes asmaller fraction of the total amount of material to be removed (<0.1microns) and produces a smooth polished surface. Semiconductor layer 16may be annealed before or after the first CMP step. The anneal step mayprovide a greater benefit in terms of layer homogenization, but atperhaps higher cost, if it is inserted between two steps of theplanarization process, e.g., between the stock and final polishingsteps. The removal of the cross-hatch by the stock polish step beforethe anneal step may allow the threading dislocations to move more freelyto the wafer edge during the anneal. Performing the final polish stepafter the anneal may be preferable for obtaining a smooth surface forthe regrowth process (see, e.g., FIG. 7). The anneal may be performed asa batch process on multiple wafers at once, for example, in a tubefurnace, to improve throughput and economics.

Referring to FIG. 8 as well as to FIG. 7, after planarization, topsurface 32 of semiconductor layer 16 may be bonded to a wafer 40.Subsequently, at least a portion of substrate 12 may be removed by,e.g., a wet etch step or a delamination process. After the removal of atleast the portion of substrate 12, at least a portion of semiconductorlayer 16 remains bonded to the wafer 40. In an embodiment, all ofsubstrate 12 may be removed, and the semiconductor layer 16 may have asecond substantially haze-free top surface 42. Second top surface 42 maybe planarized (i.e., smoothed) after removal of substrate 12.Planarizing may include chemical-mechanical polishing, plasmaplanarization, wet chemical etching, gas-phase chemical etching(preferably at elevated temperature, e.g., above 900° C., in an ambientincluding an etch species, e.g., HCl), oxidation followed by stripping,and/or cluster ion beam planarization. Wafer 40 may include a secondsubstrate 42 formed of a semiconductor, such as Si, Ge, or SiGe. Secondsubstrate 42 may also be formed of an insulating material such assapphire (Al₂O₃) or glass. Wafer 40 may also include an insulating layer44 disposed over substrate 42 and formed from, e.g., silicon dioxide.This process may be used to, e.g., prepare a semiconductor-on-insulator(SOI) substrate or an SSOI substrate.

Referring to FIGS. 7 and 9, after planarization of top surface 32 ofsemiconductor layer 16, a second layer 50 may be formed oversemiconductor layer 16. Second layer 50 may include, e.g., asemiconductor material including at least one of a group II, a groupIII, a group IV, a group V, and a group VI element, and may be formedby, e.g., CVD. Second layer 50 may have a lattice constant substantiallyequal to a lattice constant of semiconductor layer 16. Second layer 50may also be a regrowth layer formed from the same material assemiconductor layer 16. Alternatively, the lattice constant of secondlayer 50 may be substantially different from the lattice constant ofsemiconductor layer 16. The lattice constant of second layer 50 may beless than that of semiconductor layer 16, in which case second layer 50may be tensilely strained. For example, semiconductor layer 16 mayinclude Si_(1-x)Ge_(x) and second layer 50 may include Si_(1-z)Ge_(z),with z<x. In another embodiment, the lattice constant of second layer 50may be greater than the lattice constant of semiconductor layer 16, inwhich case second layer 50 will be compressively strained. For example,semiconductor layer 16 may include Si_(1-x)Ge_(x) and second layer 50may include Si_(1-z)Ge_(z), with z>x. A top surface of second layer 50may be bonded to wafer 40. Subsequently, at least a portion of substrate12 may be removed by, e.g., a wet etch step or a delamination process.After the removal of at least the portion of substrate 12, at least aportion of the second layer 50 remains bonded to wafer 40. This processmay be used to, e.g., prepare a SOI substrate or a SSOI substrate.

Referring again to FIG. 6, after annealing and planarization, topsurface 32 of semiconductor layer 16 is substantially haze-free. Haze iscaused by background scattering of a surface, and is directlyproportional to the roughness of the surface. Surface roughness mayinclude features on several different spatial wavelengths. Thecross-hatch features may typically be several micrometers (e.g., 1 μm-10μm) in wavelength, while a fine-scale roughness may also be present on ashorter length scale (<1 μm). Surface roughness may be measured byatomic force microscopy (AFM), with a tool like the Dimension 3100 fromVeeco Instruments, Woodbury, N.Y.) Haze may be measured by alight-scattering tool, such as various models of the SURFSCAN toolmanufactured by KLA-Tencor, San Jose, Calif. or the Film Inspection Tool(FIT)/Advanced Wafer Inspection System (AWIS) manufactured by ADECorporation, Westwood, Mass. In such laser-based particle or defectdetection systems for semiconductor wafers, surface roughness causes maycause light scattering, which is termed “haze.” The optical architectureof the system, i.e., the wavelength of the laser, the incident beamangle, and the polar and azimuthal angles of the collection detector(s)determines the spatial wavelengths of roughness to which the system issensitive. For example, the SURFSCAN 6220, SURFSCAN SP1-TBI dark-fieldnarrow channel with normal incidence beam (DNN), and ADE FIT/AWIS frontchannel are sensitive primarily to surface roughness features with awavelength of ˜1-10 microns, which corresponds to the cross-hatchfeature. In contrast, the SURFSCAN SP1-TBI dark-field wide channel withnormal incidence (DWN), the ADE FIT/AWIS back and center channels, andSURFSCAN SP1 dark-field narrow channel with oblique incidence (DNO) areprimarily sensitive to surface features with a spatial wavelength of <1μm, which corresponds to fine-scale roughness. Lower haze valuesindicate smoother (lower roughness) surfaces, which are generallypreferred. Haze values measured by a SURFSCAN 6220 for a high-qualitysurface are preferably less than 20 parts per million (ppm), morepreferably less than 5 ppm, and most preferably less than 1 ppm. Hazevalues measured by the ADE FIT/AWIS back and center channels or by theSURFSCAN SP1-TBI DNO channel are preferably less than 0.2 ppm and morepreferably less than 0.05 ppm.

By annealing semiconductor layer 16, the compositional variation ishomogenized. This uniform composition enables the planarization of topsurface 32, as well as cleaning of top surface 32, without there-introduction of roughness. Top surface 32 of semiconductor layer 16may, therefore, be both smooth and clean. For example, top surface 32may have a roughness root-mean-square (RMS) of less than 5 Å (in a 40μm×40 μm scan area), less than 1 Å (in a 1 μm×1 μm scan area) and acontamination level of less than 0.29 particles per square centimeter(cm²), with respect to particles having a diameter greater than 0.12 μm.This contamination level is equivalent to less than 90 localizedlight-scattering (LLS) defects greater than 0.12 μm on a 200 millimeter(mm) wafer. The roughness of top surface 32 may be less than 1 Å RMS ina 1 μm×1 μm scan area. Further, top surface 32 of semiconductor layer 16may have the following roughness and contamination levels:

Roughness root-mean-square contamination level <5 Å (40 μm × 40 μm scanarea) <0.16 particles/cm² <1 Å (1 μm × 1 μm scan area) particlediameter > 0.16 μm (<50 LLS defects on a 200 mm wafer) <5 Å (40 μm × 40μm scan area) <0.08 particles/cm² <1 Å (1 μm × 1 μm scan area) particlediameter > 0.2 μm (<25 LLS defects on a 200 mm wafer) <5 Å (40 μm × 40μm scan area) <0.0 19 particles/cm² <1 Å (1 μm × 1 μm scan area)particle diameter > 1.0 μm (<6 LLS defects on a 200 mm wafer) <3 Å (40μm × 40 μm scan area) <0.09 particles/cm² <0.5 Å (1 μm × 1 μm scan area)particle diameter > 0.09 μm

The embodiments discussed above illustrate instances in which anannealing step helps eliminate superlattices, thereby reducing surfaceroughness. In some embodiments, however, an anneal can help reduce hazeand provide a smoother layer surface even for layers which are initiallyhomogeneous, i.e., do not have superlattice or columnar compositionalvariations.

In some embodiments, growth conditions, including a first plurality ofparameters may be selected to prevent compositional superlatticeformation, thereby eliminating the need for the aforementioned anneal.The first plurality of parameters may include temperature, precursor,growth rate, and pressure. For example, a superlattice-free SiGe gradedbuffer layer may be grown at high temperatures under the followingconditions:

-   -   System: ASM EPSILON® 2000 epitaxial reactor, manufactured by ASM        International B.V., based in Bilthoven, the Netherlands    -   Temperature: 1000-1100° C.    -   Pressure: 20 Torr to 760 Torr (atmospheric pressure)    -   Hydrogen flow: 20-80 standard liters per minute (slm)    -   Dichlorosilane flow: 50-250 standard cubic centimeters per        minute (sccm)    -   Germanium tetrachloride flow: 0-0.5 gram per minute    -   Growth rate: 380-980 nm/min        In a preferred embodiment, conditions for growth of a        superlattice-free graded SiGe buffer layer may be as follows:    -   System: ASM EPSILON® 2000 epitaxial reactor    -   Temperature: 1100° C.    -   Pressure: 80 Torr    -   Hydrogen flow: 40 slm    -   Dichlorosilane flow: 250 sccm    -   Germanium tetrachloride flow: 0-0.5 gram per minute (for up to        20% Ge)    -   Growth rate: 850-980 nm/min

The presence or absence of a superlattice in a regrowth layer, e.g., aSiGe layer, formed after the planarization step should also beconsidered. Such a superlattice may be detrimental to the electricalproperties of the semiconductor layer grown on it, e.g., a strained Silayer. In some embodiments, regrowth may be performed without forming asuperlattice structure. Factors that reduce variation in a gas phasedepletion profile in, e.g., a SiGe deposition system (and therefore alsoreduce upstream-to-downstream SiGe compositional variations) tend toreduce a tendency to define a superlattice in the SiGe layer. Thesefactors include, for example, reduced dichlorosilane (DCS) or equivalentSi precursor flow/growth rate, decreased temperature, and increasedhydrogen flow rates. Conditions that produce a difference of less than5%, and preferably less than 2%, in the Ge fraction between the upstreamand downstream positions on a wafer having a diameter of 200 millimeters(mm) or less may produce superlattice-free growth. A wafer having adiameter larger than 200 mm, e.g., 300 mm or larger, may require evenless difference in the Ge fraction to achieve superlattice-free growth,e.g., possibly less than 2% variation. The effect of the conditions maybe measured by growing a wafer without rotation and measuring upstreamand downstream positions on the wafer near the wafer edge (<10 mm from awafer edge, preferably <5 mm from the wafer edge).

Like for the semiconductor layer, the regrowth layer may be formedsubstantially haze-free, and may include two elements, the two elementsbeing distributed to define a compositional variation within thesemiconductor layer. A second plurality of parameters may be used forforming the regrowth layer. These parameters may include a secondtemperature, with the first temperature used to make the semiconductorlayer being higher than the second temperature. As an example,superlattice-free regrowth of SiGe layers may be achieved in an ASMEPSILON® 2000 epitaxial reactor under the following representativeconditions:

-   -   Temperature: 700-850° C.    -   Pressure: 20-80 Torr    -   H₂ flow: 20-80 slm    -   Dichlorosilane flow: 20-60 sccm    -   Germane (GeH₄) flow: 8-34 sccm of 25% GeH    -   Growth rate: 20-200 n/min        In a preferred embodiment, conditions for superlattice-free        regrowth of SiGe layers may be as follows:    -   Temperature: 750-800° C.    -   Pressure: 80 Torr    -   H₂ flow: 40-80 slm    -   Dichlorosilane flow: 50 sccm    -   Germane flow: 17-34 sccm of 25% GeH₄    -   Growth rate: 90-100 nm/min

Referring to FIG. 10, in an alternative embodiment, the semiconductorlayer 16 may have a lower portion 100 that includes a superlattice andan upper portion 110 disposed over the lower portion 100 that issubstantially free of a superlattice. The superlattice of the lowerportion 100 may help block the effects of an underlying misfit array,thereby enabling the suppression of the reappearance of cross-hatchduring subsequent regrowth or post-planarization anneal steps.

Referring to FIG. 11, in an embodiment, second layer 50 disposed oversemiconductor layer 16 may be a regrowth layer having a lower portion150 that includes a superlattice and an upper portion 152 that issubstantially free of a superlattice. Performing the initial portion ofthe regrowth under conditions that promote the presence of thesuperlattice may block strain fields from an underlying misfit array.This enables suppression of the reappearance of the cross-hatch duringthe regrowth process or post-planarization anneal steps. A final portionof the regrowth can be performed using superlattice-free conditions asoutlined above such that the final strained Si device layer is not inproximal contact with a region having a superlattice.

In some embodiments, a “buried” region may have a superlattice, e.g.,lower portion 150 of regrowth second layer 50 or lower portion 100 ofsemiconductor layer 16, that may be annealed away after completion ofepitaxial steps.

ILLUSTRATIVE EMBODIMENTS Experimental Set 1

The following two SiGe relaxed buffer layer samples were analyzed withand without annealing:

-   1. Sample A: Non-annealed test wafer subjected to x-ray diffraction    (XRD) measurement. The Ge composition was determined to be    29.5±0.3%, with relaxation of 95.5±1%.-   2. Sample B: wafer whose Ge content was made more uniform by    annealing. After deposition, the wafer was annealed in the same    deposition chamber at 1050° C. for 5 minutes.

AFM analysis was conducted for samples A and B at different scan sizes(1 μm×1 μm, 10 μm×10 μm, and 50 μm×50 μm). Referring to Table 1,roughness values [RMS and Ra (average roughness)] were obtained. Surfaceroughness increased by an average of about 20% after annealing, based onlarge scan sizes, i.e., 10 μm×10 μm and 50 μm×50 μm. Scans of a givensize can capture roughness with wavelengths less than the scan size, butnot larger. However, characteristic RMS values represent only thewavelength with the largest amplitude, i.e., the long wavelength. Thelayers in samples A and B do not exhibit columnar decomposition.Cross-hatch roughness, i.e., waviness, increases because of the thermalannealing of the sample. The cross-hatch does not correspond to thecolumnar decomposition; rather, it ultimately arises from the influenceof the strain fields of the buried misfit dislocations in the gradedlayer. Annealing may cause the cross-hatch to reappear even after thelayer has been polished because the surface atom mobility may be high athigh temperatures. Because the buried misfit dislocations are stillpresent below the surface, the atoms on the surface may start torearrange under the influence of the misfit dislocation strain fields,bringing back a milder version of the original cross-hatch. On the otherhand, based on the small scan size that captures the short wavelengthroughness (<1 μm), the short wavelength roughness decreased by a factorof approximately seven. This significant reduction in the shortwavelength roughness reduces the haze level observed on wafers annealedlike sample B.

In some cases, annealing may reduce the short wavelength roughness andthe associated haze level of a layer, but may increase the largewavelength roughness (e.g., the cross-hatch roughness). Therefore, itmay be advantageous to perform the annealing step prior toplanarization. In this manner, the anneal reduces the propensity of theshort wavelength roughness to reappear in subsequent processing steps,and the planarization step reduces any long wavelength roughness thatreappeared during annealing. Because the re-emergence of the longwavelength roughness results from high surface atom mobility and fromatoms responding to underlying strain fields below the surface, low longscale roughness may be maintained during the annealing step in otherways. In order to reduce the surface mobility of atoms in a layer, thelayer may be capped by a protective layer. This protective layer mayinclude material that will not react with the surface being protectedand that is easily removed selectively to the underlying surface.Suitable material for the protective layer may be, for example, silicondioxide (SiO₂) or silicon nitride (Si₃N₄). The presence of theprotective layer decreases the mobility of atoms in the layer to beannealed, since the atoms no longer lie atop a free surface. Thus, ifadditional planarization is not desirable after the anneal, protectivelayers may be utilized to prevent the re-emergence of long wavelengthsurface roughness.

TABLE 1 Roughness of samples A and B at different scan sizes 1 × 1 μmscan 10 × 10 μm scan 50 × 50 μm scan Sample RMS R_(a) RMS R_(a) RMSR_(a) ID (nm) (nm) (nm) (nm) (nm) (nm) A (not 0.700 0.588 0.956 0.7742.622 1.974 annealed) B 0.103 0.083 1.151 0.945 3.471 2.213 (annealed)

Experimental Set 2

In second experiment, a SiGe graded buffer layer grown at >850° C. wasannealed at 1050° C. for 5 minutes at atmospheric pressure in hydrogen.Before and after the annealing, the surface roughness was measured byAFM with different scan sizes (1×1 μm, 10×10 μm, and 50×50 μm) at thecenter, mid-radius, and edge of the wafer. In addition, hazemeasurements using a laser defect scanner (SURFSCAN 6220, available fromKLA-Tencor) were compared between equivalent buffer layers, oneunannealed and the other annealed. Referring to Table 2, the shortspatial wavelength surface roughness derived from the 1 μm×1 μm scandecreased after the anneal by an average of about 50%. AFM images (50μm×50 μm, 10 μm×10 μm, and 1 μm×1 μm) at the edge of the wafer werecompared before and after anneal. The number of periods in thecross-hatch roughness decreased after the anneal.

TABLE 2 Roughness of samples A and B at different scan sizes Scandimension & Pre-anneal Post-anneal position R_(a) RMS R_(a) RMS 50 μm -edge 5.766 4.612 5.322 7.047 10 μm - edge 4.119 3.318 2.643 3.320  1μm - edge 0.730 1.463 0.210 0.266 0.434 0.543 0.383 0.922 0.508 0.6400.274 0.300 50 μm - mid-radius 5.588 4.560 3.942 4.950 10 μm -mid-radius 3.446 2.839 2.964 4.041  1 μm - mid-radius 0.574 0.454 0.2740.340 50 μm - center 6.189 4.957 3.641 4.689 10 μm - center 2.964 3.490 1 μm - center 0.669 0.584 0.257 0.311

Laser Particle Scanner—Haze

Surface roughness has a significant impact on the characterization ofthe buffer layers by laser particle scanning, e.g., with a TencorSURFSCAN 6220. Higher roughness is observed as elevated haze levels,making detection of small particles difficult. For this reason, one ofthe key measurements indicating the effect of a process is themeasurement of haze levels on the wafers.

Haze level measurements were made before and after the anneal of wafershaving equivalent buffer layers. The haze levels of non-annealed andannealed wafers were compared, with wafers placed in the inspection toolin the “notch down” (0 degree rotation) orientation. Haze is measured asa fraction of light energy scattered by the surface relative to theenergy in the incident laser beam. The haze level was reduced by 50% ormore by the anneal, confirming the reduction of small scale roughnessshown in the AFM data.

Another aspect of the effect of the anneal process on the wafer surfaceroughness and resulting haze measurement is the greater extent to whichthe haze of an annealed substrate is reduced by changing the orientationangle. Because fine scale roughness has a more random orientation thancross-hatch, the scattering characteristics of fine scale roughness donot depend on the orientation of the wafer in relation to the incidentbeam. The cross-hatch, in contrast, scatters the incident beam in adifferent direction depending on the orientation angle of the wafer.

Annealing the substrate increases the impact of the orientation angle onhaze. Before an anneal, changing the orientation angle of the wafer (0to 45 degrees) in the inspection system reduces the measured haze byonly about 10%, e.g., the average haze measurement is reduced from 716to 657 ppm. After the anneal, the random, fine scale roughness isreduced, and the haze is reduced by 50% when the orientation angle ischanged from 0 to 45 degrees.

Reduction of Vertical Superlattice Structure

A vertical superlattice, i.e., a vertical variation in the compositionof the SiGe, has been observed in SiGe buffer layers.

X-ray diffraction (XRD) scans of buffer layer 14 provided evidence ofthe presence or absence of superlattices in buffer layers before andafter anneal. XRD rocking curves were generated of a SiGe buffer layer14 without an anneal and with an anneal for 1050° C. for 5 minutes.Satellite peaks around the normal graded buffer signature (peaks at−3500 to −3000 arc-sec, and at +700 to +1000 arc-sec indicated thepresence of the superlattice structure in buffer layer 14 that has notbeen annealed. The peaks were observed at the wafer edge, possibly dueto the wafer edge alternating as a leading and trailing edge due towafer rotation in a horizontal flow reactor. The satellite peaks werenot present, neither at the center nor at the edge of the wafer, in aSiGe graded buffer layer 14 that has been annealed.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The foregoingembodiments are therefore to be considered in all respects illustrativerather than limiting on the invention described herein. Scope of theinvention is thus indicated by the appended claims rather than by theforegoing description, and all changes which come within the meaning andrange of equivalency of the claims are intended to be embraced therein.

1-52. (canceled)
 53. A semiconductor structure comprising: a substrate; and a semiconductor layer disposed over the substrate, the semiconductor layer including at least two elements and having a top surface, wherein the semiconductor layer top surface is substantially haze-free.
 54. The structure of claim 53 wherein a portion of the semiconductor layer disposed below the top surface comprises a superlattice.
 55. The structure of claim 53, further comprising: a relaxed graded layer disposed between the substrate and the semiconductor layer.
 56. The structure of claim 53 wherein the semiconductor layer top surface has a roughness root-mean-square of less than 5 angstroms in a scan area of 40 μm×40 μm, and a contamination level of less than 0.29 particles/cm², the particles having a diameter greater than 0.12 micrometers.
 57. The structure of claim 56 wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm.
 58. The structure of claim 53 wherein the semiconductor layer top surface has a roughness of less than 5 angstroms root-mean-square in a scan area of 40 μm×40 μm and a contamination level of less than 0.16 particles/cm², the particles having a diameter greater than 0.16 micrometers.
 59. The structure of claim 58 wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm.
 60. The structure of claim 53 wherein the semiconductor top surface has a roughness of less than 5 angstroms root-mean-square in a scan area of 40 μm×40 μm and a contamination level of less than 0.08 particles/cm², the particles having a diameter greater than 0.2 micrometers.
 61. The structure of claim 60 wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm.
 62. The structure of claim 53 wherein the semiconductor layer top surface has a roughness of less than 5 angstroms root-mean-square in a scan area of 40 μm×40 μm and a contamination level of less than 0.019 particles/cm², the particles having a diameter greater than 1 micrometer.
 63. The structure of claim 62 wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm.
 64. The structure of claim 53 wherein the semiconductor layer top surface has a roughness of less than 0.5 angstroms root-mean-square in a scan area of 1 μm×1 μm and a contamination level of less than 0.09 particles/cm², the particles having a diameter greater than 0.09 micrometers.
 65. A semiconductor structure comprising: a substrate; a semiconductor layer disposed over the substrate, the semiconductor layer including at least two elements; and a regrowth layer disposed over the semiconductor layer, the regrowth layer having a top surface, wherein the regrowth layer top surface is substantially haze-free.
 66. The structure of claim 65 wherein the regrowth layer comprises a semiconductor material.
 67. The structure of claim 66 wherein the regrowth layer comprises silicon.
 68. The structure of claim 65 wherein the regrowth layer is strained.
 69. The structure of claim 65 wherein a portion of the regrowth layer disposed below the regrowth layer top surface comprises a superlattice.
 70. A semiconductor structure comprising: a wafer, and a semiconductor layer bonded to the wafer, the semiconductor layer having a top surface, wherein the semiconductor layer top surface is substantially haze-free.
 71. The structure of claim 70 wherein the semiconductor layer comprises silicon.
 72. The structure of claim 70 wherein the semiconductor layer is strained.
 73. The structure of claim 70 wherein the semiconductor layer comprises germanium.
 74. The structure of claim 70 wherein the wafer comprises an insulating layer.
 75. The structure of claim 74 wherein the insulating layer comprises silicon dioxide. 